Process for producing trench insulation in a substrate

ABSTRACT

In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

BACKGROUND OF THE INVENTION

1. Filed of the Invention

The present invention refers to a method of producing a trenchinsulation in a substrate.

2. Description of the Related Art

In the prior art, limits are set to the application of integratedsemiconductor circuits, especially CMOS circuits, on a monocrystallinesilicon basic material, so-called bulk silicon, wafers with regard tothe use at high ambient temperatures. When power components are used,application limits result from the dissipation power of the component,which causes an increase in the crystal temperature during operation.The maximum dielectric strength that can be achieved is then limited bythe blocking property of the pn junctions and by the so-called latch-upeffect.

The cause of these limitations is essentially to be found in the factthat, in conventional circuits, the components defining the circuit areelectrically insulated from one another by blocked pn doped junctions.This has the effect that, on the one hand, a voltage limit is given bythe breakdown voltage of these pn junctions and, on the other hand, thecircuit design is subjected to restrictions insofar as pn junctionsblock only in one voltage direction, but conduct the current in theinverted voltage direction. The limitation of the maximum admissiblecrystal temperature of these components is additionally given by thesurrounding volume of the crystal material which is large in comparisonwith the volume of the actual component, e.g. the transistor. From atemperature of 130° C. onwards, the undesired transistor leakage currentcaused by the crystal temperature is no longer predominantly due to thegeneration of electron hole pairs in the space-charge zones of theblocked pn junctions themselves, but it is predominantly due to thoseelectron hole pairs which are generated in the vicinity of the pnjunction, diffuse to said pn junction and contribute to the reversecurrent.

In the prior art, it is known that these limitations can be partly orfully eliminated by introducing a dielectric insulation instead of theinsulation by means of pn junctions; in the case of such a dielectricinsulation, each of the individual components defining the integratedcircuit is fully surrounded by an insulator.

This kind of insulation is known in the prior art, but its productionnormally entails great expenditure.

For this purpose, so-called Silicon On Insulator silicon wafers (SOIsilicon wafers; SOI=Silicon On Insulator) are commercially available;when these silicon wafers are used for producing integrated circuits, adielectric insulation from the basic material is given. In this case,the basic material only serves as a mechanical support.

The lateral dielectric insulation can be achieved e.g. by the so-calledmesa technique, but with the drawback of great topographic heightdifferences after the mesa etching. This topology is not tolerablewithin modern VLSI and ULSI processes (VLSI=Very Large ScaleIntegration; ULSI=Ultra Large Scale Integration) and, without additionallevelling measures, it is therefore incompatible.

For solving the problem of lateral dielectric insulation, the so-calledtrench insulation technique has therefore become generally accepted inthe prior art. This technique comprises the step of etching a trenchinto the monocrystalline usable semiconductor layer at the smallestpossible distance permitted by the technical-physical boundaryconditions, said trench extending from the wafer surface to the boundaryof the monocrystalline usable semiconductor layer. The trench surroundsthe individual components or groups of individual components in the formof a closed boundary. For eliminating the differences in heightresulting from trench etching and for achieving a permanent insulatingproperty, it is necessary to fill the trench with an electricallyinsulating material, or to coat the trench walls with an electricallyinsulating material and to fill the residual trench withsemi-insulating, semiconductor or conductive material.

The materials that can be used for this purpose are only those which arecompatible with the subsequent semiconductor-technological productionsteps. The methods used are e.g. complete filling of the trench bythermal oxidation, partial filling of the trench by thermally oxidizingthe trench walls and additional filling of the rest of the trench e.g.by means of a silicon dioxide, doped silicon dioxide, polysilicon oramorphous silicon, which are all deposited by means of a conforminglydepositing CVD process (CVD=Chemical Vapour Deposition=chemicaldeposition from the vapour phase). If the material deposited isinsulating, also said material alone can be used for filling the trench.Normally, an anisotropic back-etching step will be necessary after theCVD process.

The above-described methods of producing a trench insulation show aplurality of disadvantages. These disadvantages are

that process control is complicated,

that individual process steps must be used, which demand a great dealfrom the equipment used and from the settings of the devices used,

that the demands with regard to process tolerances are high,

that indiviudal process steps are used, which are not compatible withthe demands to be met in the case of a CMOS production process,

that a plurality of additional lithographic steps is required,

that high demands are to be met with regard to the adjusting accuracy ofsuccessive masking steps,

that, in addition to the standard CMOS process steps to be carried out,the further steps required for producing the trench must be carried outwith a high additional expenditure, and

that a large amount of lateral space is required for the insulation.

EP 0 656 651 A2 refers to a method of producing an integrated circuitarrangement, comprising the step of producing, in a two-step trenchprocess, a trench structure in a substrate wafer. In a first etchingstep, a trench mask is produced, and, in a second etching step, thetrench structure in the substrate wafer is produced. Subsequently, thetrench structure is filled by whole-area deposition of an amorphoussilicon layer, whereby silicon spacers are formed. Following this, SiO₂spacers are formed by oxidation of the silicon spacers and the remainingspace between the spacers is filled with a silicon filling which isproduced by oxidation so as to close the trench structure by a cover.Filling of the trench is not effected by a local oxidation technique. WO93/10559 refers to a method of producing deep trenches in semiconductorsubstrates, which are filled with insulation material. A trench isetched in an appropriately prepared substrate, the walls of the trenchbeing then lined with a dielectric material in a subsequent step.Following this, a thick polysilicon layer is deposited onto the wholesubstrate, whereby also the trench is filled with the polysilicon. Itfollows that the trench is not filled by a local oxidation technique.

SUMMARY OF THE INVENTION

Starting from this prior art, it is the object of the present inventionto provide a method of producing a trench insulation in a silicon wafer,which guarantees simple process control and which carries out aplurality of necessary sub-process steps, without any additionalexpenditure, together with the standard CMOS process steps that have tobe carried out anyway.

The present invention provides a method of producing a trench insulationin a silicon wafer. The method has the steps of depositing a firstsilicon-oxide layer on a ore manufactured sequence of layers on thefront surface of a silicon wafer, structuring the first silicon-oxidelayer so as to define a mask for a subsequent production of a trench,etching a trench having a predetermined depth in the silicon wafermaking use of said mask, filling the trench with a silicon oxide,conforming deposition of a first polysilicon layer on the firstsilicon-oxide layer and on the oxide-filled trench, removing the firstpolysilicon layer in such a way that a polysilicon cover remains on saidoxide-filled trench and removing the first silicon-oxide layer.

In comparison with the prior art described hereinbefore, the presentinvention provides a plurality of advantages, viz.

that process control is simple;

that individual process steps are used, which demand as little aspossible from the equipment, said process steps permitting thus theproduction of a trench insulation in a manner which is as simple aspossible and simultaneously reliable,

that individual process steps are used, which demand as little aspossible from the setting of the machines,

that the demands to be met by the process tolerances are as low aspossible (large process windows),

that indiviudal process steps are used, which are compatible with thedemands to be met in the case of a CMOS production process,

that only a single additional lithographic step is required,

that no unusually high demands are to be met by the adjusting accuracyof successive masking steps and that constrained mask derivatives arenot necessary,

that the temporal succession of the additional steps which are specificto trench production is chosen such that subtasks are automaticallycarried out, without any additional expenditure, together with standardCMOS process steps which are to be carried out anyhow,

that little lateral space is required for the insulation,

that future advantages in comparison with known methods can be seen,when in the course of the foreseeable technical development thelithographic dimensions used in production will be reduced stillfurther.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, a preferred embodiment of the present invention willbe described in detail on the basis of the drawings enclosed, in which:

FIG. 1 shows a semiconductor substrate having the trench formed in itsfirst main surface.

FIG. 2 shows the semiconductor substrate after the trench fillingprocess.

FIGS. 3 and 4 show the semiconductor substrate after a polysilicondeposition process of the substrate of FIG. 2.

FIGS. 5 and 6 show the semiconductor substrate after plasma etching ofthe polysilicon layer.

FIG. 7 shows the semiconductor substrate of FIG. 6 after the removal ofthe oxide layer.

FIG. 8 shows the semiconductor layer of FIG. 7 after structuring thesilicon nitride layer.

FIG. 9 shows the semiconductor substrate of FIG. 8 after a fieldoxidation.

FIG. 10 shows the semiconductor substrate of FIG. 9 after a completeremoval of the silicon nitride layer.

FIG. 11 shows the semiconductor substrate of FIG. 10 after removal of apredetermined thickness of the silicon oxide layer.

FIG. 12 shows the semiconductor substrate of FIG. 11 after oxidation inan oxygen atmosphere.

FIG. 13 shows the semiconductor substrate of FIG. 12 after removal ofthe oxide layer.

FIG. 14 shows the semiconductor substrate of FIG. 13 after growing agate oxide on exposed silicon surfaces.

FIG. 15 shows the semiconductor substrate of FIG. 14 after deposition ofa polysilicon layer.

FIG. 16 shows the semiconductor substrate of FIG. 15 after doping,structuring, and etching the polysilicon layer.

FIG. 17 shows the semiconductor substrate of FIG. 16 after theproduction of source/drain regions.

FIG. 18 shows the final semiconductor substrate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is pointed out that identical reference numerals have been used inall figures for corresponding layers, components etc.

The first embodiment of the method according to the present inventiondescribed hereinbelow deals with a trench insulation technique in thecase of which the layer thickness remaining in the SOI wafer islaterally separated by means of a trench around the component. Thetrench is etched from the surface down to the insulator layer locatedbelow the active crystal layer and it is filled with insulating materialso that, at the end, a largely planar surface of the overall arrangementor total circuit is obtained.

The starting wafer used for the embodiment described hereinbelow is aspecial kind of SOI wafer, viz. a so-called BESOI wafer (BESOI=BackEtched Silicon On Insulator), which is offered by an increasing numberof manufacturers all over the world. The BESOI wafer 100 (see FIG. 1)has a front surface 100 a which is commonly polished and thereforeprepared for manufacturing semiconductor devices (further called front),and a back surface 100 b which is commonly dull and used formechanically supporting the wafer during manufacturing and handling(further called back). The trench is formed in the front.

In the technical development taking place in this field there is agrowing trend towards an availability of a wafer with increasingly smalllayer-thickness tolerances and, consequently, thin usable layers whichbecome smaller and smaller and which can be produced in large-scalemanufacturing processes.

The advantage in comparison with an alternative production method for anSOI wafer is the good crystal quality of the usable layer, the qualityand the variation possibilities of the silicon dioxide layer locatedbelow said usable layer and the comparatively low price.

For the embodiment described hereinbelow, a BESOI wafer is used, whichhas a usable layer thickness of approx. 2±0.5 μm and a thickness of 2 μmof the silicon dioxide layer (SiO₂ layer) located below said usablelayer on the front.

This material was commercially available at the time of the presentinvention.

Wafer with thinner usable layer thickness with correspondingly smallerthickness tolerances, which will be available in the future, will beadvantageous for the sequence of process steps in low-power applicationsdescribed hereinbelow, with regard to improved component properties andless complicated process control.

The BESOI material used in accordance with this preferred embodiment hasin a usable layer (bond) a specific resistance of 17 to 33 Ω cm, whichis adjusted to this value with regard to the properties which thetransistor produced is desired to have at the end of the process.

In a first process stage I, the production of a non-structured layersequence is prepared.

In a first method step S1, a prenitride oxide layer or pad oxide layerhaving a thickness of 40 nm grows on the front of the BESOI wafer, whichis referred to as sequence of layers in the following, at a temperatureof 950° C. in a dry, oxygenous atmosphere.

In a second method step S2, a nitride layer having a thickness of 100 nmis deposited on the front and on the back of the sequence of layers bymeans of an LPCVD process (LPCVD=Low Pressure Chemical VapourDeposition=low pressure deposition from the gaseous phase).

In a third method step S3, an oxide layer is deposited on the nitridelayer, which has been applied to the front and to the back of thesequence of layers, by means of an TEOS-LPCVD process(TEOS=tetraethylorthosilicate). The oxide layer is deposited with athickness of 200 nm and is also referred to as deposited oxide layerwhich serves to protect the surface of the nitride layer applied inmethod step S2.

In a fourth method step S4, the nitride layer is removed from the backof the sequence of layers. The deposited oxide serves here as aprotection against contamination when, during etching of the back of thesequence of layers, the front of the sequence of layers rests on thesupport or chuck of the etching system.

Wet etching of the back of the sequence of layers by means of aconventional basin immersion process cannot be carried out directly,since production-compatible organic cover layers are not resistant tothe hot phosphoric acid.

The demands on the selectivity of this etching process are very low. Itis only necessary that the deposited oxide layer (step S3) and thenitride layer (step S2) are etched fully through.

Excessive etching into the carrier silicon which is comprised in thesequence of layers and which has a thickness of at least 0.5 mm isundetrimental when it occurs as a result of the non-uniformity caused byvery simple machines.

In a fifth method step S5, the sequence of layers is cleaned.

In a sixth method step S6, the deposited oxide layer on the front of thesequence of layers is removed by immersion of the sequence of layersinto an etching solution containing hydrofluoric acid. The etchingsolution containing hydrofluoric acid is used due to the highselectivity of the hydrofluoric acid (HF) with regard to the nitridelayer. Subsequently, the sequence of layers is rinsed with deionizedwater, dried and tempered at 750° so as to remove adsorbed watermolecules.

In a seventh method step S7, a first oxide layer is deposited with athickness of 470 nm on the nitride layer, which has been deposited instep S2, by means of an TEOS LPCVD process. This oxide layer serves as aso-called hard mask for a subsequent trench etching.

The aim of the process stage I described hereinbefore was the productionof a laterally initially still unstructured layer 100, as shown in theright half of FIG. 1. The sequence of layers 100 comprises

a monocrystalline silicon carrier wafer 102;

a buried silicon dioxide layer 104 (SiO₂ layer);

a thinned monocrystalline usable component layer 106;

a standard pad oxide layer 108 for stress equalization during thesubsequent local oxidation;

a silicon nitride layer 110 (Si₃N₄ layer) for forming a nitride maskduring a subsequent local oxidation;

a deposited silicon dioxide layer (SiO₂ layer) 112 which serves as amask or hard mask during a subsequent trench etching process.

On the back of the layer structure 100 there is now only the depositedsilicon dioxide layer (SiO₂ layer)—which is not shown.

In a subsequent process stage II, the silicon dioxide layer 112 isstructured as a trench mask and the trench is etched.

In an eighth method step S8, a photoresist is applied to the first oxidelayer 112. It is pointed out that the narrower the trench can be etched,the shorter and the more advantageous the subsequent process sequencewill be. The technical progress of future process generations will havea positive influence on the final result that can be achieved.

In a ninth method step S9, the mask or hard mask is etched. For thispurpose, the photoresist layer applied in method step S8 is structuredin an appropriate manner and, at the points at which the trench is to beproduced, the exposed deposited oxide layer 112 is etched by means of ananisotropic oxide plasma etching process down to the monocrystallineusable silicon layer 106.

It is pointed out that this plasma etching process for silicon dioxideis a standard technique, which is frequently used e.g. for openingcontact holes when silicon circuits are being produced.

The small selectivity with regard to nitride, which is a characteristicof dry oxide etching processes, has the effect that the nitride layer110 is structured as well. This is here a desired effect. Excessiveetching into the usable silicon layer 106 is at this point undetrimentalto the desired final result.

In a tenth method step S10, the still remaining photoresist layer isremoved by means of an oxygen plasma treatment after the structuring ofthe mask or hard mask. In addition, it may also be necessary to removeresidual polymers with a wet-chemical stripper.

In an eleventh method step S11, the actual trench 114 is etched into themonocrystalline usable layer 106 by means of an anisotropic chloroplasmadry etching process.

Reference is made to the fact that the above-described anisotropicchloroplasma dry etching process is used e.g. for structuringpolysilicon gate electrodes or in an etching process of the type usedfor producing trench cells in the case of dynamic RAMs (RAM=RandomAccess Memory).

The structured oxide layer 112 on the surface of the sequence of layers100 serves here as a masking layer.

The buried thermal silicon dioxide layer 104 serves here as an etch stopin the depth of the trench.

The selectivity of a chloroplasma etching process is approx. 10:1 to20:1, i.e. the etching rate in silicon is ten times higher than that inSiO₂. This guarantees a large process window, which permits toleranceswith regard to the etching time, the etching rate and the lateraluniformity over the sequence of layers 100.

The structure obtained after process stage II is shown in FIG. 1.

A process stage III only comprises the twelfth method step S12 in whichthe trench 114 is filled by oxidation.

An essential feature of the present invention is to be seen in the factthat, while the trench 114 is being filled by oxidation, the structureddeposited oxide layer 112 “hard mask” remains unchanged on the sequenceof layers 100.

The sequence of layers is now subjected to oxidation in a thermaloxidation process in a water-vapour atmosphere until the trench 114 hasfilled up. It is a characteristic feature of this thermal oxidation thatthe resultant layer thicknesses are produced in approximately equalparts by consumption of the oxidized silicon and by the oxygen suppliedfrom outside. The oxidation time must therefore be adjusted at leastsuch that an oxide layer thickness corresponding in size to the singlewidth of the trench grows on a simultaneously oxidized bare siliconwafer. When the trench width is 1 μm, this being a width that canreliably be achieved by today's lithographic processes, an oxide layerof 1 μm thickness must grow. When the trench width is 0.8 μm, this beinga width that can be achieved by modern exposure processes, it will,analogously, suffice when an oxide layer of 0.8 μm thickness grows. Thismakes evident that the present trend towards smaller dimensions insemiconductor technology provides a technical advantage in the case ofthis method in contrast to filling methods by means of conformingdeposition from the vapour phase, which would correspond to the priorart.

In the case of non-ideal, i.e. not fully reaction-limited, conformingdepositions processes, it may easily happen that the part of the trenchlocated closer to the surface is filled more rapidly than the partlocated further down. This has the consequence that the trench willalready be closed on the upper side, whereas a capillary cavity, aso-called pipe cavity, remains in the lower part.

The oxidation-filling process used for the embodiment described in thepresent connection is almost ideally reaction-limited in the case of theexisting geometries and will certainly not result in pipe cavities whenthe trench does not have any negative flank angles.

During the progressive thermal oxidation of silicon, the oxygen mustdiffuse through the SiO₂ layer, which has already grown, to thesilicon-SiO₂ boundary surface. The chemical reaction will not take placeuntil this boundary surface has been reached. Diffusion barriers, likethe remaining deposited oxide layer 112 of the hard mask and most of theSi₃N₄ layer according to the embodiment described in the presentconnection, make it possible that the local oxidation used here resultsin conforming uniform filling of the trenches alone.

The oxidation-filling process of the trench walls is self-limiting,since the replenishing of oxygen from the oxidation atmosphere isautomatically reduced by orders of magnitude as soon as the layer frontsfrom both sides of the trench contact each other in the middle.

The condition of the sequence of layers 100 resulting from the trenchfilling process is shown in FIG. 2. The SiO₂ layer 116 on the trenchwalls has grown under half the originally existing mask delimiting thetrench. The broken line 113 in FIG. 2 shows the dimensions of theoriginal trench 114.

On the upper side of the new lateral boundary of the trench, theso-called “birdsbeak”, 114 a which has been known for a long time fromlocal oxidation technology (LOCOS), has formed below the Si₃N₄ layer 110and bent the mask upwards, i.e. away from the front of the sequence oflayers, at the edge thereof.

On the boundary surface of the silicon carrier layer 102 locatedopposite the trench some oxide has additionally grown; this results inthe bulge 118 of the buried oxide layer 104 shown in FIG. 2.

The two phenomena described last and the edge rounding at the lower sideof the trench originate from the oxygen diffusion mechanisms describedhereinbefore.

In the middle of the now filled trench, two problem areas can be seen;in view of these problem areas this initially simple method could not beused easily.

The first problem area is the so-called “gusset” 120 on the upper sideof the sequence of layers 100. During the subsequent process steps,remnants of chemicals and particles may collect in this gusset; during apolysilicon gate process, remains of polysilicon may unintentionallyform conducting paths which may cause short circuits and, consequently,failures of the circuit in question. The second problem area is thepossibly still existing “seam” 122 at which the two oxide layers 116have grown together. Due to capillary effects, etching acid solutionscontaining hydrofluoric acid may penetrate into this seam, the use ofthese etching acid solutions being unavoidable in the field of CMOStechnology. Once this etching solution has penetrated, it is almostimpossible to remove and, due to undesired etching corrosion, it willcause permanent damage during the future manufacturing process and,later on, in the finished circuits.

A feasible method of removing the hard mask again is not known. In spiteof their high selectivity with regard to Si₃N₄, etching solutionscontaining hydrofluoric acid cannot be used, since they would preferablyattack in the area of the gusset 120 and thus partly defill the trench.

Anisotropic oxide etching processes are too unselective with regard toSi₃N₄ and would not alter the disadvantageous profile of the gusset.

Reference is made to the fact that different oxidation methods orcombinations of known oxidation methods can be used for filling thetrench with an oxide. A first possible method is the filling the trenchwith an CVD oxide. Another possibility is filling by means of thermaloxidation. In accordance with still another possibility, the trench canbe filled partly by means of thermal oxidation and the rest of thetrench can be filled with a CVD oxide, or vice versa.

In a subsequent process stage IV, the disadvantages describedhereinbefore are eliminated.

In order to avoid the problems arising from the filling of the trench, alayer 124 of undoped polysilicon is deposited, immediately afterwardswithout any further intermediate step, from the gaseous phase in aconformingly working LPCVD process in a thirteenth method step S13.

A polysilicon deposition process is a constituent part of any modernpolysilicon gate total process and is therefore known in the productionfield in question.

The use is here unproblematic, since edges having overhanging flanks(negative flank angle) do not exist in the present case. For the etchedtrench width of 1 μm, a deposited layer thickness of 0.7 to 0.8 μmproves to be expedient. The production state which has now been reachedcan be seen in FIG. 3 and FIG. 4, respectively.

It is pointed out that this step of conforming deposition of thepolysilicon is an important feature of the method according to thepresent invention.

By means of the conforming deposition process, it was first of allpossible to round off the pointed, disadvantageous topography in thearea of the gusset 120 and, simultaneously, it was possible to reducethe differences in height on the front of the sequence of layers 100.

Although this is not shown in FIGS. 3 and 4, a polysilicon layer wasalso deposited on the back of the sequence of layers 100 by means of thepolysilicon deposition process.

In a fourteenth method step S14, the polysilicon layer is removed fromthe back of the sequence of layers 100 over the whole area. This is doneby means of a plasma etching process. During this etching process, thefront surface of the sequence of layers 100 of the wafers is positionedon the chuck of the etching system.

The deposited oxide, which was also applied to the back of the sequenceof layers 100 in method step S7, serves as an etch stop layer.

In a fifteenth method step S15, the deposited polysilicon layer 124 isetched away by means of an anisotropic chloroplasma etching processwithout any further intermediate step and without making use of a mask.This can be done in the same system which is used for structuring gateelectrodes, or it can be the same system which was used for etching thetrench.

The selectivity of this silicon etching process is in the range of 1:10to 1:20 with regard to the deposited oxide layer 112 remaining on thefront surface of the sequence of layers 100.

It follows that a reliable etch stop and immunity to a nonuniformitywhich is normally entailed by this type of production process are given.

The Si₃N₄ layer is 110 therefore preserved undamaged.

The anisotropic etching process uniformly removes the layer to be etched124 predominantly in a direction perpendicular to the wafer surface.

FIG. 5 shows the resultant levelling effect of the back-etching of thepolysilicon layer 124. The original surface is here represented by abroken line.

FIG. 6 shows the condition of the sequence of layers 100 when methodstep S15 has been finished.

As can be seen from FIG. 6, the application of the above-describedanisotropic back-etching step S15 has the effect that the trench gusset120 is levelled and that a polysilicon cover 124 a is formed on theoxide-filled trench 114.

Reference is made to the fact that the formation of the polysiliconcover 124 a on the oxide-filled trench 114 is an essential feature ofthe present invention.

In a method step S16, the remaining mask is now removed by simplewet-chemical basin immersion etching in a solution containinghydrofluoric acid.

The back of the sequence of layers 100, which must be renderedhydrophobic, serves as a monitor for the end of the etching process.

Etching solutions containing hydrofluoric acid have a selectivity of atleast 1:100 with regard to silicon as well as with regard to Si₃N₄.

It follows that the hard mask, which consists of the deposited oxidelayer 112, can be removed without any difficulties.

The condition of the sequence of layers 100 after the removal of thedeposited oxide layer is shown in FIG. 7.

The method of producing a trench insulation according to the presentinvention has been described on the basis of process stages I to IVdescribed hereinbefore.

By means of this method, a trench filled with insulating material hasbeen produced on the one hand, and, on the other hand, said trench hassimultaneously been covered completely and partially levelled making useof a material that is largely resistant to the wet-chemical etchingsolutions which contain hydrofluoric acid and which are unavoidable in aCMOS process. In comparison with conventional methods, the followingadvantages are therefore achieved:

the mask required for etching the trench can easily be removed,

the trench is filled with silicon dioxide, but is still covered in thisproduction state in such a way that CMOS-compatible and necessarywet-chemical etching and cleaning steps can be used in the way in whichthey are normally used in this kind of production process, withoutjeopardizing the integrity of the trench filling, and

the Si₃N₄ layer has been preserved so that after the production stateshown in FIG. 7 the final integrated circuit can be produced by means ofa conventional sequence of CMOS process steps.

Reference is made to the fact that, in the most negative case, theremaining polysilicon cover 124 a covering the trench projectsrelatively far beyond the front surface of the sequence of layers. Thisis, however, only a momentary intermediate state, since the following,conventional sequence of CMOS process steps comprises a plurality ofoxidation steps and selective oxide etching steps which result in alargely planar surface of the sequence of layers 100 at the end of theprocess.

Subsequently, the final integrated circuit is completed in a processstage V.

In a seventeenth method step S17, which concerns a phototechnique forstructuring the Si₃N₄ layer 110 so as to produce thick oxide areas bymeans of local oxidation, conventional dry etching of the Si₃N₄ layer iscarried out.

The production state is shown in FIG. 8.

For taking into account also the worst case, it has been assumed for thecontinued process that, due to the “shade effect” of the polysiliconcover 124 a of the trench 114, an Si₃N₄ edge 126 remains as a result ofthe anisotropic nitride etching process.

Prior to an eighteenth method step, some doping material predepositionsteps by means of ion implantation and resist masks are carried out inthe CMOS production process, said predeposition steps being known per seamong those skilled in the art.

In the case of a widely used process family, it is common practice thatthe local oxidation for producing the thick oxide areas is preceded by asimilar LOCOS subprocess module by means of which the definition of theglobal n- and p-doped regions can be carried out in a self-adjustingmanner (the so-called twin-tub process).

This complicated process module can be dispensed with when the trenchinsulation according to the present invention is used. In the embodimentdescribed in the present connection, the trench was etched with a widthof 1 μm, the width of the trench in the filled condition being 2 μm.When the global n- and p-doped regions are defined by means of resistimplantation masks and when the resist edge is placed onto the middle ofthe respective trench when the mask is being designed, the sum of theedge error and of the adjustment error may be ±1 μm.

This value can easily be achieved by means of the stepper lithographytechnique which is widely used today.

The higher expenditure entailed by the trench insulation technique istherefore partly compensated for by the above-described possibility ofsimplifying the process.

In an eighteenth step S18, a field oxidation is carried out e.g. in ahumid oxygen atmosphere at 1000° C. The aimed-at oxide thickness is heree.g. 650 nm.

As can be seen from FIG. 9, also the trench cover 124 a projectingbeyond the front of the sequence of layers 100 has been oxidized (cf.layer 130) in addition to the oxidation of the monocrystalline silicon106 (SiO₂ layer 128).

Approx. 350 nm of the trench cover 124 a has been consumed for formingthe oxide 130 at the trench-cover surfaces exposed to the atmosphere.

In a subsequent nineteenth method step S19, the nitride oxidation mask110 is fully removed. This is normally done by means of a wet-chemicalimmersion etching process in hot phosphoric acid at 160° C.

The production state is shown in FIG. 10. FIG. 10 also shows that alsothe possibly still existing Si₃N₄ residues (126, FIG. 9) at the edges ofthe trench cover 124 a, 130 have been eliminated.

Subsequently, the sequence of layers 100 is carefully rinsed indeionized water.

As can be seen in FIG. 10, the pad oxide layer 108, which was protectedby the nitride layer 110 during the field oxidation process in step S18,is no longer covered due to the removal of said nitride layer 110.

In a twenty-first method step S21, the prenitride oxide layer (pad oxidelayer) 108 is etched. For this purpose, a predetermined layer thicknessis removed uniformly from all SiO₂ surfaces 128, 108 in a wet-chemicalimmersion etching process in an etching solution containing hydrofluoricacid.

The aim is to etch in the thin oxide areas (132, FIG. 11) down to thebare monocrystalline silicon of the usable silicon layer 106.

Subsequently, careful rinsing in deionized water is carried out.

The production state obtained is shown in FIG. 11.

In a twenty-second method step S22, the now exposed mono-crystallinesilicon layer is oxidized in a humid oxygen atmosphere at 1000° C. so asto suppress the so-called “white ribbon” artifact.

The aim is to obtain an oxide thickness of 100 nm on the bare silicon.

FIG. 12 shows the resultant condition, which, in principle, does notdiffer from the condition shown on the basis of FIG. 10.

This step is also referred to as “sacrificial oxidation step”.

In a twenty-third method step S23, the “sacrificial oxide layer” isremoved. This is done by removing a predetermined layer thickness fromall SiO₂ surfaces in a wet-chemical immersion etching process in etchingsolutions containing hydrofluoric acid. The aim is to etch in the thinoxide area down to the bare monocrystalline silicon of the usablesilicon layer 106.

The hydrophobicity of the back of the sequence of layers, which occurredat the end of the process, can be used as a monitor in said twenty-thirdmethod step.

Subsequently, careful rinsing in deionized water is carried out.

FIG. 13 shows the production state obtained, which, in principle, doesnot differ from the state shown in FIG. 11.

It is, however, pointed out that repeated etching of the wholesilicon-dioxide surfaces will reduce the SiO₂ percentage of the trenchcover.

In a twenty-fourth method step S24, a gate oxide 134 having a thicknessof e.g. 55 nm is caused to grow on the exposed silicon surfaces by meansof an oxidation process in a dry oxygen atmosphere at e.g. 950° C.

The production state, which does not differ from FIGS. 12 and 10 in apurely visual sense, is shown in FIG. 14.

In a twenty-fifth method step S25, threshold voltage implantation takesplace. This implantation, which is known per se, does not have anyinfluence on the trench. At the end, a normally 5 nm thick oxide layeris uniformly removed in a wet-chemical process in connection with thenecessary cleaning steps.

In a twenty-sixth method step S26, a polysilicon layer 136 is depositedon the SiO₂ layer 128 and the trench cover 124 a, 130 as well as on thegate oxide layer 134.

This deposition is carried out by means of the same system which hasbeen used for depositing the first polysilicon layer 124 with the aid ofa conforming LPCVD process.

The resultant production state is shown in FIG. 15. The conformingdeposition process causes levelling of the surface of the sequence oflayers 100 in the area of the edges of the trench cover.

In a twenty-seventh method step S27, the polysilicon deposited in step26 is doped, since, after having been structured, this polysiliconserves as a gate electrode. Phosphorus doping from the gaseous phase isrequired for making the polysilicon layer 136 sufficiently conductive.

In a twenty-eighth method step S28, structuring of the polysilicon gateelectrodes is carried out. The structuring is effected through aphotoresist mask by means of the anisotropic chloroplasma dry etchingprocess which has already been used twice in the course of the precedingprocess steps.

The underlying silicon dioxide layer 128 and the thin gate oxide layer134, respectively serves as an etch stop during this dry etchingprocess.

The selectivity of this process relative to silicon dioxide is approx.1:20.

The process is known per se among those skilled in the art andconstitutes a standard process in the field of MOS technology.

FIG. 16 shows the resultant production state.

On the left-hand side, part of a polysilicon conducting path 138 onfield oxide is shown, whereas on the right-hand side a gate electrode140 on thin gate oxide 134 is shown.

In the middle, the effect which this step S28 has on the shape of thetrench cover can be seen. The drawing is true to scale with regard tothe layer thickness and the lateral dimensions in the trench area. Itcan be seen that the topography in the area of the trench cover showsdifferences in height which are only slightly larger than those in theareas of the gates and polysilicon conducting paths. The topography inthe two last-mentioned areas is known per se and all the manufacturersof semiconductors must tolerate it, or they rather have to takeappropriate levelling measures so to facilitate the subsequent processsteps.

As can be seen from FIG. 16, a part 142 of the polysilicon layer 138deposited in step S26 also remains in the area of the trench cover.

A twenty-ninth method step S29 deals with the production of source-drainregions or with source-drain technology in general.

In this step, a plurality of resist implantation maskings, ionimplantations and intermediate cleaning and oxidation steps, and, ifdesired, also a spacer technology for producing the n- andp-source/-drain islands and the ohmic contacts to the global n- andp-doped regions, are carried out.

The effects, with the exception of the doping profiles produced, areshown in FIG. 17.

It can only be seen that the polysilicon areas 138, 140, 142 underwentthermal oxidation on the basis of which an oxide layer 144 grew.

In a thirtieth method step S30, an intermediate insulator is depositedand levelling is caused by flow distribution of said intermediateinsulator.

In addition to the thermal oxide layer 144 which is already present onthe polysilicon layer 138, 140, 142, an additional intermediateinsulator, first an undoped deposited oxide layer, e.g. the depositedoxide layer used as a hard mask at the beginning, and subsequently anSiO₂ (PBSG) doped with phosphorus and boron in the percent range, isdeposited from the gaseous phase.

The PBSG 146 can make the steep flanks of the polysilicon edge lesssteep in a flow-distribution step at a temperature of e.g. 900° C. (Cf.FIG. 18).

This will make the side walls of the trench cover less steep so that thesubsequent opening of contact holes and the so-called process “back end”can fully be carried out in the manner known per se among those skilledin the art.

It is pointed out that the method described hereinbefore is a preferredembodiment of the present invention.

The method steps which are essential to the method according to thepresent invention do, however, not include all the above-mentionedmethod steps.

According to the first embodiment, the method according to the presentinvention comprises essentially the method step S7 in the course ofwhich a first oxide layer 112 is deposited on the front of a sequence oflayers 100 including the SOI substrate (cf. FIG. 1); the method steps S8to S10 in the course of which the first oxide layer 112 is structured soas to define a mask for a subsequent production of a trench (FIG. 1);the method step S11 in the course of which a trench is etched down tothe oxide layer of the SOI substrate making use of the mask (FIG. 1);the method step S12 in the course of which the trench 114 is filled withan oxide (FIG. 2); the method step S13 in the course of which a firstpolysilicon layer 124 is deposited on the first oxide layer 112 and onthe oxide-filled trench 114 (cf. FIG. 4); the method step S15 in thecourse of which the first polysilicon layer 124 is removed in such a waythat a polysilicon cover 124 a remains on the oxide-filled trench 114;and the method step S16 in the course of which the first oxide layer 112is removed (cf. FIG. 7).

Reference is also made to the fact that, although the preferredembodiment of the present invention uses a so-called BESOI substrate, itis also possible to use SOI substrates that have been produced by meansof other methods.

In the following, further preferred embodiments of the presentinvention, which differ from the first preferred embodiment with regardto some method steps, will be described in detail.

In accordance with a second preferred embodiment of the presentinvention, the method steps S4 to S6 for removing the nitride layer fromthe back of the sequence of layers 100 are carried out as followshereinbelow.

In connection with this embodiment, the oxide layer deposited in step S3is used as an etching mask for the nitride of the nitride layer 110 tobe protected on the front surface of the sequence of layers 100.

In a step 4.1, the front surface of the sequence of layers 100 has aresist applied thereto and the deposited oxide layer on the back of thesequence of layers 100 is removed by immersion in an etching solutioncontaining hydrofluoric acid.

In a method step S4.2, the resist on the front surface is removed andthe nitride layer on the back is removed by immersion into hotphosphoric acid, the deposited oxide layer on the front surface of thesequence of layers 100 acting as an etching mask during this step.

In a method step S4.3, the sequence of layers 100 is rinsed withdeionized water and in the subsequent method step S4.4phosphorus-contaminated oxides on the front and on the back of thesequence of layers 100 are removed in an etching solution containinghydrofluoric acid.

Subsequently, renewed rinsing with deionized water takes place in amethod step S4.5, and the sequence of layers 100 is cleaned in a methodstep S4.6. In a method step S4.7, renewed rinsing with deionized waterand drying of the sequence of layers 100 are carried out.

In the final method step 4.8, the sequence of layers 100 is tempered at750° C. so as to remove adsorbed water molecules.

According to a third embodiment of the present invention, the methodsteps following hereinbelow are carried out instead of the method stepsS3 to S6.

In a method step S3′, the back of the sequence of layers 100 is etchedin a modern spin-etching machine, e.g. an RST 100, RST 200 of SEZ.

Finally, the sequence of layers 100 is tempered at 750° C. in a methodstep S4′ so as to remove adsorbed water molecules.

According to a fourth embodiment of the present invention, the methodstep S14 in the course of which the polysilicon layer on the back of thesequence of layers 100 is removed over the whole area is carried out bywet-chemical back etching on a modern spin-etching machine.

The present invention is, however, not limited to the use of SOIsubstrates. On the contrary, the invention is also applicable to simplesubstrates, i.e. in a so-called bulk material.

In the following, a fifth embodiment will be described briefly;according to said embodiment, a trench insulation is produced in asimple substrate. The method according to the fifth embodiment differsfrom that of the first embodiment essentially insofar as a simplesubstrate is used instead of an SOI substrate, the trench having apredetermined depth being etched into said simple substrate.

In accordance with said fifth embodiment, the method according to thepresent invention comprises essentially the following method steps:

in a first method step, a first oxide layer is deposited on a frontsurface of a sequence of layers including the substrate. Following this,the first oxide layer is structured so as to define a mask for thesubsequent production of a trench. When the mask has been defined, atrench is etched into the substrate making use of the mask, said trenchhaving a predetermined depth. The depth of the etched trench is adjustede.g. by the duration of the etching process or by controlling otherparameters of the etching process, this being known per se among thoseskilled in the art. When the trench has been etched, it is filled withan oxide and a first polysilicon layer is deposited on said first oxidelayer and on the oxide-filled trench. Following this, the firstpolysilicon layer is removed in such a way that a polysilicon coverremains on the oxide-filled trench. Finally, the first oxide layer isremoved.

The method according to the fifth embodiment results in a trenchinsulation which permits the active components to be arranged in closerrelationship with one another, i.e. to be packed more closely, than thiswould be possible in the case of the so-called LOCOS insulation.Furthermore, the insulating properties obtained when the methodaccording to the present invention is used are better than thoseobtained in the case of LOCOS insulation.

The trench insulation according to the fifth embodiment is used e.g. inthe field of 256-megabit or larger DRAMs and for logic processes thatcan be derived from these memories.

What is claimed is:
 1. A method of producing a trench insulation in asilicon substrate, said silicon substrate having a first main surfaceand a second main surface, comprising the following steps; a) depositinga first silicon-oxide layer, a first silicon nitride layer, and a secondsilicon-oxide layer in this order on the first main surface of thesilicon substrate; b) structuring the first silicon-oxide layer, thefirst silicon nitride layer, and the second silicon-oxide layer so as todefine a mask for a subsequent formation of a trench; c) etching atrench in the silicon substrate making use of said mask; d) filling saidtrench by a local oxidation of silicon (“LOCOS”) process by subjectingthe structure formed by step (a) to (c) to an oxidation in a thermaloxidation process for growing on the trench walls silicon oxide layersuntil the silicon oxide layers grown on the trench wall contact eachother, thereby completely filling the trench with a silicon oxide; e)conforming deposition of a first polysilicon layer on the secondsilicon-oxide layer and on the oxide-filled trench; f) removing saidfirst polysilicon layer in such a way that a polysilicon cover remainson said oxide-filled trench; and g) removing the second silicon-oxidelayer.
 2. The method according to claim 1, wherein the silicon substrateis an SOI substrate, and in step c) etching of the trench is effecteddown to an insulating layer of the SOI substrate.
 3. The methodaccording to claim 1, wherein the trench is etched by means of achloroplasma dry etching process.
 4. The method according to claim 1,wherein the second silicon-oxide layer is deposited by a TEOS LPCVDprocess.
 5. The method according to claim 1, wherein the firstpolysilicon layer is deposited by means of an LPCVD process.
 6. Themethod according to claim 1, wherein the first polysilicon layer isremoved by means of an etching process.
 7. The method according to claim1, wherein the second silicon-oxide layer is removed by a wet-chemicaletching process.
 8. A method of producing a trench insulation in a SOL,said SOI having a first main surface and a second main surface,comprising the following steps: a) depositing a first silicon-oxidelayer, a first silicon nitride layer, and a second silicon-oxide layerin this order on the first main surface of the SOL substrate; b)structuring the first silicon-oxide layer, the first silicon nitridelayer, and the second silicon-oxide layer so as to define a mask for asubsequent formation of a trench; c) etching a trench down to aninsulating layer of the SOI substrate making use of said mask; d)filling said trench by a local oxidation of silicon (“LOCOS”)process bysubjecting the structure formed by step (a) to (c) to an oxidation in athermal oxidation process for growing on the trench walls silicon oxidelayers until the silicon oxide layers grown on the trench wall contacteach other, thereby completely filling the trench with a silicon oxide;e) conforming deposition of a first polysilicon layer on the secondsilicon-oxide layer and on the oxide-filled trench; f) removing saidfirst polysilicon layer in such a way that a polysilicon cover remainson said oxide-filled trench; and g) removing the second silicon-oxidelayer.
 9. A method of producing a trench insulation in a siliconsubstrate, said silicon substrate having a first main surface and asecond main surface, comprising the following steps; a) depositing afirst silicon-oxide layer, a first silicon nitride layer, and a secondsilicon-oxide layer in this order on the first main surface of thesilicon substrate; b) structuring the first silicon-oxide layer, thefirst silicon nitride layer, and the second silicon-oxide layer so as todefine a mask for a subsequent formation of a trench; c) etching atrench in the silicon substrate making use of said mask; d) filling saidtrench by a local oxidation of silicon (“LOCOS”) process by subjectingthe structure formed by steps (a) to (c) to an process selected from thegroup consisting of: filling said trench by CVD oxide deposition; orfilling said trench partially by thermal oxidation and filling theremainder of said trench by CVD oxide deposition; thereby completelyfilling the trench with a silicon oxide; e) conforming deposition of afirst polysilicon layer on the second silicon-oxide layer and on theoxide-filled trench; f) removing said first polysilicon layer in such away that a polysilicon cover remains on said oxide-filled trench; and g)removing the second silicon-oxide layer.